PLL design and investigation in CMOS

Abstract

In the article the architecture of a charge pump phase locked loop is shown. The influence on overall system performance of its functional blocks is discussed. Voltage controlled oscillator phase noise analysis is done and the relationship between a charge pump phase locked loop and voltage controlled oscillator phase noises are determined. The requirements and results of the accomplished design are discussed. Area of chip PLL – 150×250 μm2, power consumption – 10 mW and phase noise is –125 dBc/Hz with 1 MHz deviation from central 670 MHz frequency.

Article in Lithuanian.

Fazės derinimo kilpos integrinio grandyno projektavimas ir tyrimas

Santrauka. Pateikti reikalavimai fazės derinimo kilpos su krūvio pompa integrinio grandyno architektūrai ir išnagrinėti svarbiausi jos funkciniai blokai. Atlikta įtampos valdomo generatoriaus fazinių triukšmų analizė, aptarta parametrų priklausomybė nuo geometrinių matmenų ir jų įtaka visos sistemos triukšmams. Fazės derinimo kilpos integrinio grandyno lusto plotas lygus 150×250 µm 2 , suvartojama galia – 10 mW, o fazinis triukšmas –125 dBc/Hz esant 1 MHz nuokrypiui nuo centrinio 670 MHz dažnio.

Reikšminiai žodžiai: fazės derinimo kilpa, įtampa valdomas generatorius, fazinis triukšmas, integrinis grandynas.

Keywords:

phase locked loop, voltage controlled oscillator, phase noise, integrated circuit, CPPLL

How to Cite

Charlamov, J. (2010). PLL design and investigation in CMOS. Mokslas – Lietuvos Ateitis Science – Future of Lithuania, 2(1), 54-58. https://doi.org/10.3846/mla.2010.012

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February 28, 2010
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Published

2010-02-28

How to Cite

Charlamov, J. (2010). PLL design and investigation in CMOS. Mokslas – Lietuvos Ateitis Science – Future of Lithuania, 2(1), 54-58. https://doi.org/10.3846/mla.2010.012

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